Senior RTL / Digital IC Design Engineer

About the Role
We are seeking a Senior RTL / Digital IC Design Engineer to develop high-performance digital logic for Optical DSP (ODSP) and communication ASIC products. The successful candidate will be responsible for RTL implementation, micro-architecture development, integration, and silicon bring-up support for next-generation optical interconnect devices.

Key Responsibilities
·      Develop synthesizable RTL using Verilog/SystemVerilog for high-performance DSP, datapath, control, and interface blocks.

·      Translate architectural and algorithm specifications into efficient micro-architecture implementations.

·      Own RTL development from specification through coding, integration, synthesis support, and tapeout.

·      Design high-speed, low-latency, and power-efficient digital logic for communication and optical networking applications.

·      Collaborate closely with architecture, DSP, verification, physical design, DFT, and firmware teams.

·      Drive RTL quality through lint, CDC, reset-domain analysis, and design reviews.

·      Support synthesis, timing closure, power optimization, and PPA trade-off analysis.

·      Debug functional and integration issues during simulation, emulation, FPGA prototyping, and silicon bring-up.

·      Develop and maintain design documentation, micro-architecture specifications, and coding guidelines.

·      Mentor junior RTL engineers and contribute to design methodology improvements.

Requirements:

·      Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related fields.

·      5+ years of experience in ASIC/SoC RTL design.

·      Strong understanding of digital design fundamentals, micro-architecture, pipelining, timing, and clocking concepts.

·      Experience participating in one or more successful ASIC tapeouts.