SOC Design Engineer

* Fresh  graduates are welcome to apply

Job Responsibilities:-

• Design digital logic with high-level description language (VHDL/Verilog) from specification
• Design quality RTL that meets all design requirement of input/output requirements, constraints, multiple clock domains, functional modes, and analog blocks
• Design RTL with Low power requirement from standard power intent file input
• Design of RTL for SoC and FPGA-friendly and DFT compliant code is critical
• Design of RTL for IP development and SoC assembly
• Design of RTL for SoC Clock & Reset structures is a plus
• Verify the design through extensive test-bench simulation and ability to debug with FPGA prototyping
• Experience with Design For Test requirement is a plus
• Experience with Synthesis, and Logic Equivalent checks are added advantage
• Work with other RTL2netlist and Backend team to resolve any design issues

Job Requirements:-

• Bachelor Degree/Master's in Electrical/Electronics Engineering with an emphasis in IC design
• Experience in the complete cycle of DSM (65, 45, 40, 28, 16nm) SoC Design, verification and tape-out experience of several million-gates-count complex SoC together with validation of silicon is essential
• Previous development experience in one or more of these areas: GPS, WLAN, BT, NFC, Ethernet, SoC/ARM/AHB bus design is a plus
• Expert knowledge of Low power input standard like UPF/CPF and SoC connectivity tools e.g. Core Consultant, etc. has a strong advantage
• Experience through IC life cycle from conception, design, verification, tapeout and silicon validation
• Able to work in a multi-cultural team with a strong drive to excel
• Able to work independently on a given assignment and work hard to finish on time
• Good written and communication skills

Location: Next to Bendemeer MRT

Interested candidatesmay submit detailed CV with the following info:-

• Current salary, including AWS or Variable Bonus
• Expected salary
• Availability