Interface IP Architect

We are representing our client an IC Design platform company to hire for

Interface IP Architect

Job Responsibilities

• Conduct competitive analysis, roadmap planning, and specification formulation for MIPI M-PHY 20G+, Gear 4, UFS, and other multimedia interface IPs.
• Develop and deliver in-house multimedia interface PHY IPs, achieving targeted performance, power, and area (PPA) indicators.
• Design and implement PHY IP architecture for multimedia interfaces.
• Design and implement test pieces, packaging, test board, and perform post-silicon bring-up and testing.
• Collaborate with the back-end team to complete physical implementation of PHY IPs and ensure timing closure.

Job Requirements

• Minimum Degree in Electrical / Electronic engineering or its equivalent with around 10 years of experience in Multimedia, Inter-Chip or Storage Interface IP design and successful tape-out
• Over 5 years of experience in Multimedia, Inter-Chip, or Storage IP architecture design.
• Proven track record in developing advanced Multimedia, Inter-Chip, or Storage technology IPs.
• Familiarity with IC High-Speed Interface IP market, competitive landscape, and experience in product road mapping and definition.
• Preferably familiar with standards such as M-PHY, UFS, and their predecessors.
• Candidates with experience in MIPI, UFS, and other subsystem development, tape-out, debugging, and successful mass production will be prioritized.
• Strong communication skills, high sense of responsibility, commitment to delivery, and excellent team collaboration abilities.

Interested applicants, kindly forward a copy of your updated resume in WORD document to [email protected] stating your current and expected remuneration together with notice period required by current employer.

EA License No: 12C6254 | EA Personnel Registration No: R1879665