Technical Manager – NPU Physical Design

Job Requirements:

Bachelor’s in EE/ECE (or a related field). 10 years in APR layout implementation and CAD/automation development.Deep CMOS layout knowledge across planar/FinFET/GAA, incl. DRM/DFM. ExpertPV/debugging (Caliber, PVS, or equivalent). Strong scripting: Python, Tcl, SKILL, Perl. Knowledge of floorplanning/power mesh/criticalrouting/hierarchical integration. Strong cross-team communication. Hands-onproficiency with APR tools: Cadence Innovus, Synopsys ICC2, and/or Fusion Compiler. Plus: AI/Agentic AI in EDA, Foundation IP (IO/ESD), RF/Analog layout,SI/PI, EM/IR.

Technical Manager – NPU Physical Design (APR & CAD Automation)

Location: Singapore
Employment Type: Full-Time
Industry: Semiconductor | AI Hardware | ASIC | VLSI | EDA

Shape the Future of AI-Driven Physical Design

Are you passionate about combining advanced physical design with intelligent design automation? We are looking for a Technical Manager – NPU Physical Design (APR & CAD Automation) to lead the development of next-generation physical implementation methodologies for AI accelerator and NPU technologies.

This role offers a unique opportunity to combine deephands-on expertise in ASIC Physical Design (APR) with CAD automation, workflow optimization, and AI-powered EDA innovation. You will work across multiple engineering teams to develop scalable physical design solutions for advanced semiconductor technologies while driving automation that improves productivity, quality, and tapeout success.

Key Responsibilities

As a Technical Manager, you will play a key technicalleadership role by:

Physical Design Implementation

• Lead complete ASIC physical implementation for Foundation IP, Analog IP, RFIC, and digital design blocks.
• Perform full-cycle Automatic Place & Route (APR) using industry-leading EDA tools such as:

• Cadence Innovus

  Synopsys IC Compiler II (ICC2)

  Fusion Compiler

• Drive:

• Floorplanning

  Power mesh planning

  Cell placement

  Clock implementation

  Hierarchical integration

  Routing optimization

• Optimize designs for Power, Performance, and Area (PPA) while ensuring high-quality silicon implementation.

CAD Automation & Methodology Development

• Own and enhance automated physical design flows covering APR, Physical Verification, and signoff.
• Design and maintain scalable CAD infrastructure, reusable templates, parameterized cells (P-Cells), and modular implementation architectures.
• Develop automation frameworks using Python, Tcl, SKILL, and Perl to improve engineering productivity.
• Standardize physical design methodologies and best practices across multiple engineering programs.
• Provide centralized CAD support for project teams and continuously improve design workflows.

AI-Powered EDA Innovation

• Drive adoption of AI and Agentic AI technologies to accelerate physical design automation.
• Identify opportunities to improve layout productivity, optimization, and design quality through intelligent automation.
• Collaborate with engineering teams to implement next-generation AI-assisted EDA methodologies.

Physical Verification & Signoff

• Execute and debug Physical Verification flows, including:

• Design Rule Check (DRC)

  Layout Versus Schematic (LVS)

  Electrical Rule Check (ERC)

  Antenna Checks

  PERC Verification

• Ensure robust sign-off by addressing:

• Signal Integrity (SI)

  Power integrity (PI)

  Electromigration and IR Drop (EM/IR)

  Electrostatic Discharge (ESD)

Requirements

Required Qualifications

• Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• Minimum 10 years of experience in both:

• ASIC Physical Design (APR/Layout Implementation)

  CAD Automation and Design Methodology Development

• Deep knowledge of CMOS layout across:

• Planar

  FinFET

  Gate-All-Around (GAA) technologies

• Strong understanding of:

• Design Rule Manuals (DRM)

  Design for Manufacturability (DFM)

• Expert-level experience with Physical Verification and debugging using tools such as:

• Siemens Calibre

  Cadence PVS

  Equivalent verification platforms

• Advanced scripting and automation skills in:

• Python

  Tcl

  SKILL

  Perl

• Strong expertise in:

• Floorplanning

  Power mesh design

  Critical routing

  Hierarchical physical implementation

• Hands-on experience with one or more leading APR tools:

• Cadence Innovus

  Synopsys ICC2

  Fusion Compiler

• Excellent communication, collaboration, and stakeholder management skills.

Preferred Qualifications

Experience in any of the following will be highly advantageous:

• AI or Agentic AI applied to EDA and physical design automation
• Foundation IP, IO, or ESD implementation
• RFIC or Analog Layout
• Signal Integrity (SI) and Power Integrity (PI) analysis
• EM/IR optimization and signoff
• Advanced semiconductor technology nodes (5nm, 3nm, 2nm, and beyond)

Why Join Us?

• Work at the forefront of AI hardware and semiconductor innovation.
• Influence next-generation AI-powered EDA and physical design methodologies.
• Lead cutting-edge implementation projects for advanced process technologies.
• Collaborate with world-class engineers on complex NPU and AI accelerator designs.
• Drive engineering excellence through automation, innovation, and technical leadership.
• Enjoy competitive compensation, career advancement opportunities, and exposure to the latest semiconductor technologies.

Ready to Build the Future of AI Silicon?

If you're an experienced Physical Design and CAD Automation expert who thrives on solving complex engineering challenges and advancing AI-driven design methodologies, we would love to hear from you.

Apply now and help shape the future of intelligent semiconductor design.