AI Chip Front-End Design Lead (NPU)

About Bitdeer:

Bitdeer Technologies Group (Nasdaq: BTDR) is a world-leading technology company for Bitcoin mining. Bitdeer is committed to providing comprehensive computing solutions for its customers. The Company handles complex processes involved in computing such as equipment procurement, transport logistics, datacenter design and construction, equipment management, and daily operations. The Company also offers advanced cloud capabilities to customers with high demand for artificial intelligence. Headquartered in Singapore, Bitdeer has deployed datacenters in the United States, Norway, and Bhutan.

Role Overview: Responsible for end-to-end management of Neural Processing Unit (NPU) and SoC design, including team leadership, module implementation, and full process optimization.

What you will be responsible for:

• Lead the overall architecture definition and module-level microarchitecture design of NPU/SoC.
• Oversee SoC top-level and core module logic design, implementing high-performance IP using Verilog/SystemVerilog (such as matrix computation units, memory controllers, and on-chip network NoC).
• Lead IP/SoC synthesis, DFT design, and back-end handoff.
• Responsible for the development of NPU subsystems, including the design and verification of key components such as Tensor/Vector computing units and data paths.
• Work closely with algorithm, architecture, and toolchain teams to analyze AI model characteristics (e.g., CNN/Transformer) and optimize parallel computing strategies.

How you will stand out:

• Over 8 years of SoC development experience and 3+ years of NPU development experience. Capable of independently handling complex module design. Candidates with complete AI chip tape-out experience are preferred.
• In-depth understanding of CNN/Transformer models and computing logic, with strong knowledge of hardware mapping and system-level performance optimization (e.g., memory bandwidth, computing efficiency).
• Deep understanding of AI algorithms and data processing workflows.
• Proficient in Verilog and C; familiar with UVM verification methodology. Experienced with Linux OS and front-end EDA tools such as Spyglass, Design Compiler (DC), PrimeTime (PT), VCS from Synopsys/Cadence/Mentor. Skilled in scripting languages such as Tcl, Perl, Python.
• Strong logical thinking, communication, and teamwork skills. Able to perform under pressure.
• Familiar with GPU/NPU heterogeneous architectures; experienced with bus protocols (e.g., AXI) and memory controller design or debugging.
• Master’s degree or above in Electrical Engineering, Microelectronics, or related field.

What you will experience working with us:

• A culture that values authenticity and diversity of thoughts and backgrounds;
• An inclusive and respectable environment with open workspaces and exciting start-up spirit;
• Fast-growing company with the chance to network with industrial pioneers and enthusiasts;
• Ability to contribute directly and make an impact on the future of the digital asset industry;
• Involvement in new projects, developing processes/systems;
• Personal accountability, autonomy, fast growth, and learning opportunities;
• Attractive welfare benefits and developmental opportunities such as training and mentoring.