Automotive High-Speed Interface Design Architect

Job Description

1. Lead the design and development of High-Speed Interface PHY IP for automotive products.

2. Design automotive-grade high-speed serialiser and deserialiser interface PHY with focus on low-power RX, EMI robustness, and high-reliability clock architectures.

3. Develop competitive analog circuit specifications and architectural solutions, drive technical innovations and breakthroughs to meet stringent reliability requirements.

4. Oversee the functional, performance, reliability, and testability of the design and verification for analog and mixed-signal ICs.

5. Integrate built in self-test solutions to the High-Speed PHY IP to enable full IP integrity checks in fully autonomous vehicles.

6. Develop top-level floorplans for analog designs and guide layout engineers through the implementation phase.

7. Continuously monitor industry trends in high-speed interface PHY architectures and design to promote innovation.

Requirements

1. Master’s degree or above in Electronics, Communications, Computer Engineering or related fields.

2. Experience in high-speed mixed-signal interface design including but not limited to CTLE, DFE, CDR, Driver, PLL, and ADC/DAC is preferred.

3. Prior experience in system-level design, including system architecture definition and analog module specification setting, is a plus.

4. Experience with advanced process nodes and tape-out processes is preferred.

5. Proven experience in team leadership or cross-functional collaboration.

6. Proficient in automotive-grade design verification tools, fault injection analysis, and reliability simulation.

7. Quick learner with a passion for innovation and exploring new technical frontiers.

8. Strong team player with a rigorous, optimistic, and proactive attitude.