Lead engineer -Design verification

Requirements

What you need to have to be successful

• BSEE /MSEE 8 -12 years Degree of experience in block, sub -system, and full -chip verification
  
• Should have delivered multiple chips functioning to Specification.
  
• Identify and manage verification deliverables, milestones, and schedules.
  
• Proactively identify potential verification risks and develop mitigation strategies.
  
• Collaborate with design, architecture, and software teams to understand and verify design intent.
  
• Communicate verification progress, issues, and results to stakeholders and management.
  
• Strong in understanding multiple architectures, integrating 3rd party IPs/VIPs, and working with mixed -signal designs with low -power design and verification challenges
  
• Strong understanding/exposure to Design Verification for low -power battery -operated designs is highly desired.
  
• C -based verification in an SoC environment is required
  
• Experience with ARM processor -based designs and low -power design techniques is a plus.
  
• Languages: SystemVerilog (UVM), Verilog, C/C++, Python, Perl or Makefile
  
• Technologies: ARM M/RISC -V (Preferred), AMBA AXI/AHB/APS, DMA, Flow Control, Serial Devices, Qo5
  
• Preferred technologies: MIPI(CSI/DSI), Crypto, OTP, DSP, Low -Power