RTL Design Engineer

• Understanding
  design specification and performing RTL design of the IP using Verilog/System
  Verilog
  
• Perform design
  verification, formal verification and code coverage analysis of the IP
  
• Understanding
  timing constraints to ensure that the IP passes post -layout simulation
  
• Create clear
  and precise documentation for the design
  
• Support
  post -silicon validation effort
  

Requirements

• Understanding
  design specification and performing RTL design of the IP using Verilog/System
  Verilog
  
• Perform design
  verification, formal verification and code coverage analysis of the IP
  
• Understanding
  timing constraints and applying right timing constrints
  
• Create clear
  and precise documentation for the design
  
• Support
  post -silicon validation effort