Senior Analog Layout Design Engineers - Competitive Pay

Roles & Responsibilities

Job Description:

• Work with IC Design engineer to design and layout custom RF, analog and mixed-signal circuits from sub-blocks to top-level integration and verification.
• Perform physical design verifications (LVS/DRC/ERC).
• Collaborate with IC Design engineers to optimize layout implementation for better power, performance and area.
• Responsible for full-chip physical verification sign-off and tape-out.
• Good understanding of semiconductor and circuit design.

Job Requirements:

• Bachelor degree in Electrical and Electronics Engineering or equivalent.
• At least three (5+ ) or more years of RF, analog /mixed custom IC physical design experience.
• Experience with schematic-driven layout, floor planning, chip level routing, design rule and physical verification, and chip integration.
• Good understanding of critical device matching, high voltage layout techniques, advanced node Pmos/ Nmos guarding.
• Good knowledge of design manuals.
• Good Knowledge of CAD tools (Cadence Virtuoso, Mentor Calibre DRC/LVS/ERC, Synopsys Hercules, Cadence PVS).
• Must have good analysis and troubleshooting skills.
• Should be able to work independently, self-motivated, have a good team spirit, a strong sense of responsibility and urgency, be a creative problem solver, and be hardworking.
• Good communication skills in written and verbal English.

Skills & Competencies:

• Outstanding career growth and development opportunities
• Competitive salary & work benefit package
• Passionate, energetic & innovative work culture