Senior Engineer HIG PSE IE Wafer Reliability Operation

Facilitate and lead weekly triage meetings with Probe Operations and Site IE Planning to align on: Tester availability Probe card readiness Wafer allocation and production planning Turn-Around-Time (TAT) compliance and issue resolution Wafer Reliability Scheduling Develop and maintain wafer loading plans based on forecast and site capacity. Coordinate with flex cap and probe card teams using IE modeling tools. Execute tactical planning for wafer shipments across sites based on multiple lots execution strategies Capacity & Resource Planning Collaborate with NPI, MH, and PE teams to consolidate HBM roadmap requirements. Build and manage capacity loading plans and dashboards for pre-qual NPI execution Monitor tester and probe card activity, ensuring that usage is recorded and MOR capacity is planned effectively for reporting needs. Process & System Coordination Translate engineering requests into executable test flows in MAM/MES systems. Ensure compliance with RAS audits and QA standards. Support debug system setup and operation for ELFR and Rel Ops Cross-Functional Collaboration Liaise with Fab, IE Planning, and Media Health teams to ensure alignment on wafer-level engineering cycles of learning. Drive for lot staging analysis, and sampling plan execution Bachelor's degree in Engineering or related field. 5+ years of experience in semiconductor reliability operations or process engineering. Strong proficiency in MAM/MES systems, project management, and equipment planning. Excellent communication and stakeholder management skills. Experience with tactical planning and inventory management in a lab or manufacturing setting.