SoC Design Verification Lead - Join a Leading Company

About the Job

Join our dynamic verification team dedicated to pushing the boundaries of innovation. As a Design Verification Lead, you'll play a pivotal role in our quest for excellence, utilizing cutting-edge verification methodologies across diverse design landscapes, including UVM, C/C++ co-simulation, system emulation, mixed-mode simulation, and formal verification. 

Our mission is clear: achieving zero defects through the most efficient and intelligent approaches in the expansive realm of verification.

Description

As a SoC design verification lead, you are expected to carry out the following responsibilities.

1. Be in-charge of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification.
2. Conduct thorough test plan reviews systematically and execute the plan on-time with high quality.
3. Achieve zero-defect with the best and smartest approach to the large verification space.

Requirements

1. Strong expertise in UVM verification methodology.
2. Highly disciplined, quality-minded, and highly driven for excellence.
3. Excellent team player and good communication skills.
4. MSEE/BSEE in Electrical Engineering or Computer Engineering, with at least 10 years of relevant experience.
5. Candidates with relevant experiences would be offered as either Staff, Sr. Staff, or Verification Manager by taking on higher responsibilities.
6. Experience in video processing and video analytics is a plus.
7. Passionate and strong in general programming is a plus.

Interested candidates kindly click the APPLY NOW button.

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EnviroDynamics Solutions Pte Ltd (EDS)

EA License No.: 12C6285